The present invention relates to a method of controlling the voltage threshold (Vt) distribution utilizing a pulse width during the operation of a plurality of non-volatile multi-level memory cells, and more particularly, to non-volatile multi-level memory cells having a two-bit per cell storage layer. The method is applicable to the operations of programming and erasing non-volatile multi-level memory cells, such as, but not limited to, nitride trapping memory and PHINES cells.
Non-volatile multi-level memory refers to types of semiconductor memories that maintain stored information when a power source is not applied to the memory. Some examples of non-volatile memory cells include Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM) and Electrically Erasable Programmable Read-Only Memory (EEPROM). Typically, non-volatile memory cell data can be programmed, read and/or erased, and the programmed data can be stored for long periods of time prior to being erased.
Nitride read only memory (nitride trapping memory) is a type of EBEPROM memory that uses charge-trapping for data storage. An nitride trapping memory cell is typically composed of a metal-oxide-silicon field effect transistor (MOSFET) having a top dielectric layer, such as an ONO (oxide-nitride-oxide) layer disposed between a gate and a substrate with source and drain regions in a portion of the semiconductor substrate material. The nitride material in the ONO top dielectric layer has the capability to “trap” charges (electrons) when the cell is “programmed.” Charge localization is the ability of the nitride material to store the charges without significant lateral movement of the charges throughout the nitride layer, thus the charges are independent to the other. A typical nitride trapping memory cell utilizes a relatively thick tunnel oxide layer, which typically negatively influences the time it takes to erase a memory cell. The nitride trapping memory cell can be contrasted with conventional “floating gate” memory cells, wherein the floating gate is conductive. However, the charge is free to spread laterally throughout the entire floating gate, and charge is transferred through the tunnel oxide layer. Programming (e.g., charge injection) of the charge-trapping layer in nitride trapping memory cells can be carried out by various hot carrier injection methods such as channel hot electron injection (CHE), source side injection (SSI) or channel initiated secondary electron (CHISEL), both of which inject electrons into the nitride layer. Localized charge-trapping technology allows two separate charge bits per cell, thus resulting in a doubling of memory density per cell.
The erasing operation (i.e., charge removal) is preformed by applying a positive gate voltage, which permits hole tunneling through the ONO top dielectric layer from the gate. Erasing in nitride trapping memory cells are typically carried out by band-to-band hot hole tunneling (BTBHHT). However, BTBHHT erasing causes many reliability issues and degradation of the nitride trapping memory cells by increasing charge losses after many program/erase operation cycles.
The reading operation is carried out in either a forward or a reverse direction. Reading a nitride trapping memory cell does not affect the cell data. The nitride trapping memory cell can be repeatedly programmed, read and erased by known voltage application techniques.
A PHINES memory cell is another type of nitride trapping storage non-volatile memory, which uses an n-channel MOSFET with a modified ONO top dielectric layer. The PHINES memory cell typically uses a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) cell structure, which is arranged in a NAND array with the charges stored in the nitride layer. A PHINES memory cell utilizes two physical bits of storage, and thus has advantageous capabilities in high scaling applications. Other advantages for the PHINES cell are that it has low power requirements and provides better data retention over many programming/erasing operations throughout its life as compared to similar two-bit non-volatile memory cells.
For PHINES cells, techniques such as Fowler-Nordheim (FN) injection and band-to-band hot-hole injection (BTBHHT) are typically used for erasing and programming operations, respectively. Erasing a PHINES cell uses FN injection, which exhibits a self-convergent behavior without creating over-erasing issues while maintaining efficiency. The programming is done by lowering the local voltage threshold (Vt) through the BTBHHT injection technique. Low (Vt) state leakage can be controlled and suppressed in a PHINES cell via a bit-by-bit program and verify technique. The programming and erasing operations for the PHINES memory cell are low power operations, which are ideal for mass storage applications that are often complex in design.
The voltage threshold (Vt) of the non-volatile memory cell is proportional to the amount of charge that is retained in the charge storage layer. As the charge changes, the voltage threshold changes to a different level. The voltage thresholds define the program levels of the multi-level memory cells that correspond to program states. The program states represent binary data stored in the memory cells.
A multi-level non-volatile memory cell is implemented by identifying multiple and distinct voltage threshold ranges within the cell. Each distinct voltage threshold range corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the voltage threshold levels of the cell depends upon the programming operation scheme adopted for the cells. To achieve proper data storage for a multi-level memory cell, the multiple ranges of voltage thresholds should be separated from each other by sufficient margin so that the level of the memory cell can be programmed or erased in an unambiguous manner. The voltage threshold separations from each level define a distribution within the cell that corresponds to the program levels and program states. By controlling the voltage threshold distributions, the threshold margins are less likely to encroach on the program levels, thereby eliminating any problems with the voltage threshold affecting the others.
When electrons accumulate in the charge storage layer, the layer becomes negatively charged and the voltage threshold of the memory cell rises to a higher level. The tighter the voltage threshold distribution, the easier it is to unmistakably read the memory cells. The need for controlling the voltage threshold distributions is even more important with multi-level memory cells, because the read process needs to distinguish between the different voltage threshold distributions without resulting in errors. To control the voltage threshold distribution, a pulse width method is used to program the memory cells.
Prior art methods for controlling the voltage threshold (Vt) distribution require more complicated techniques than that of the present invention. U.S. Pat. No. 6,219,276 (Parker) and U.S. Pat. No. 6,320,786 (Chang et al.) disclose methods that requires the use of multiple programming voltages for achieving multiple voltage threshold (Vt) distributions, which increases the design complexity, wherein the programming voltages are not constant. In addition, Parker teaches a method of utilizing a number of pulses to control the voltage threshold distribution. Specifically, the greater number of pulses used to program a cell, the narrower the voltage threshold (Vt) distribution. In contrast, the method of the present invention utilizes the pulse width and not the number of pulses to control the voltage threshold (Vt) distribution.
Additionally, U.S. Pat. No. 6,396,741 (Bloom et al.) discloses a method utilizing a stepping of the drain voltage to program the non-volatile memory cell. This method increases the design complexity for controlling program voltages since the voltages are not constant during the programming operation.
U.S. Pat. No. 6,172,909 (Haddad et al.) discloses a method to tighten the threshold voltage distribution curve in a memory cell. Haddad is directed to a soft-programming method, wherein the soft-programming method is applied after an erase operation to avoid over-erase issues, thereby controlling the Vt distribution. Furthermore, Haddad does not control the voltage threshold distribution of each memory cell by varying a pulse width of a programming pulse that is applied to each memory cell. In contrast, the present invention utilizes a program method that controls the Vt distribution for different Vt levels by varying a pulse width of a programming pulse applied to each memory cell.
The prior art methods cited above, rely on more complex designs that are less efficient and more costly to implement, which impinge on the overall MLC operation and effectiveness of the non-volatile memory cell, regardless of whether one uses nitride trapping memory or PHINES cells. Moreover, the prior art methods do not consider issues related to the over-programming and over-erasing of memory cells, wherein these issues have a detrimental effect on the memory cell's charge retention as well as the cell's life cycle.